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| CY2303 Phase-Aligned Clock Multiplier Features Functional Description The CY2303 is a 3 output 3.3V phase-aligned system clock designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance applications. The part allows user to obtain 1x, 2x, and 4x Ref output frequencies on respective output pins. The CY2303 has an on-chip PLL, which locks to an input clock presented on the REFIN pin. The PLL feedback is internally connected to the REF output. The input-to-output skew is guaranteed to be less than 200 ps, and output-to-output skew is guaranteed to be less than 200 ps. Multiple CY2303 devices can accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is guaranteed to be less than 400 ps. The CY2303 is available in commercial and industrial temperature ranges. 3-multiplier configuration (1x, 2x, 4x Ref) 10 MHz to 166.67 MHz operating range (reference input from 10 MHz to 41.67 MHz) Phase Alignment 80 ps typical period jitter Output enable pin 3.3V operation 5V Tolerant input 8-pin 150-mil SOIC package Commercial and Industrial Temperature available Selector Guide Part Number CY2303SXC CY2303SXI Outputs 3 3 Input Frequency Range 10 MHz-41.67 MHz 10 MHz-41.67 MHz Output Frequency Range 10 MHz-166.67 MHz 10 MHz-166.67 MHz Specifics Commercial Temperature Industrial Temperature Logic Block Diagram FBK x1 PLL x2 REF REFIN REFx2 x4 OE REFx4 Cypress Semiconductor Corporation Document #: 38-07249 Rev. *C * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised September 23, 2008 [+] Feedback CY2303 Pinouts Figure 1. CY2303 - 8-pin SOIC Top View REF GND REFIN N/C 1 2 3 4 8 7 6 5 OE VDD REFx4 REFx2 Pin Description Pin 1 2 3 4 5 6 7 8 REF GND REFIN N/C REFx2 REFx4 VDD OE Signal[1] REF output (1x Reference input) Ground Input reference frequency, 5V tolerant input No Connect 2x Reference input 4x Reference input 3.3V Supply Output Enable (weak pull up) Description Maximum Ratings Supply Voltage to Ground Potential................-0.5V to +7.0V DC Input Voltage (Except Ref) .............. -0.5V to VDD + 0.5V DC Input Voltage REFIN........................................ -0.5 to 7V Storage Temperature ................................. -65C to +150C Junction Temperature ................................................. 150C Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................. >2000V Operating Conditions for CY2303SC Commercial Temperature Devices Parameter VDD TA CL CIN tPU Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, Fout < 133.33 MHz Load Capacitance, 133.33 MHz < Fout < 166.67 MHz Input Capacitance Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Description Min 3.0 0 - - - 0.05 Max 3.6 70 18 12 7 50 Unit V C pF pF pF ms Electrical Characteristics for CY2303SC Commercial Temperature Devices Parameter VIL VIH IIL IIH VOL Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage [2] Test Conditions Min. - 2.0 Max. 0.8 - 100 50 0.4 Unit V V A A V VIN = 0V VIN = VDD IOL = 8 mA - - - Notes 1. Weak pull-down on all outputs. 2. Parameter is guaranteed by design and characterization. It is not 100% tested in production. Document #: 38-07249 Rev. *C Page 2 of 7 [+] Feedback CY2303 Electrical Characteristics for CY2303SC Commercial Temperature Devices VOH IDD Output HIGH Voltage[2] Supply Current IOH = -8 mA Unloaded outputs, REFIN = 41.67 MHz Unloaded outputs, REFIN = 25 MHz Unloaded outputs, REFIN = 10 MHz 2.4 - - - - 45 32 18 V mA mA mA Switching Characteristics for CY2303SC Commercial Temperature Devices Parameter 1/t1 Name Output Frequency Duty Cycle t3 t4 t5 t6 t7 tJ tLOCK Rise Fall [3] Test Conditions 18-pF load 12-pF load Measured at VDD/2 Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V All outputs equally loaded Measured at VDD/2 Min 10 - 40 - - - - - - - Typ. - - 50 - - - - - 80 - Max 133.33 166.67 60 1.20 1.20 200 200 400 175 1.0 Unit MHz MHz % ns ns ps ps ps ps ms = t2 / t1 Time[3] Time[3] Output to Output Skew on rising edges[3] Delay, REFIN Rising Edge to Measured at VDD/2 from REFIN to any output REF Rising Edge[3] Device to Device Skew[3] Period Jitter[3] PLL Lock Time[3] Measured at VDD/2 on the REF pin of the device (pin 1) Measured at Fout < 133.33 MHz, loaded outputs, 18-pF load Stable power supply, valid clocks presented on REFIN Operating Conditions for CY2303SI Industrial Temperature Devices Parameter VDD TA CL tPU Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, Fout <133.33 MHz Load Capacitance, 133.33 MHz < Fout < 166.67 MHz, Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Description Min. 3.0 -40 - - 0.05 Max. 3.6 85 15 10 50 Unit V C pF pF ms Electrical Characteristics for CY2303SI Industrial Temperature Devices Parameter VIL VIH IIL IIH VOL VOH IDD Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage[2] Output HIGH Voltage Supply Current [2] Test Conditions Min - 2.0 Max. 0.8 - 100 50 0.4 - 48 35 20 Unit V V A A V V mA mA mA VIN = 0V VIN = VDD IOL = 8 mA IOH = -8 mA Unloaded outputs, REFIN = 41.67 MHz Unloaded outputs, REFIN = 25 MHz Unloaded outputs, REFIN = 10 MHz - - - 2.4 - - - Note 3. All parameters are specified with loaded outputs. Document #: 38-07249 Rev. *C Page 3 of 7 [+] Feedback CY2303 Switching Characteristics for CY2303SI Industrial Temperature Devices Parameter 1/t1 Name Output Frequency Duty Cycle[3] = t2 / t1 t3 t4 t5 t6 t7 tJ tLOCK Rise Time [3] Test Conditions 15-pF load 10-pF load Measured at VDD/2 Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V All outputs equally loaded Measured at VDD/2 Min 10 - 40 - - - - - - - Typ. - - 50 - - - - - 80 - Max 133.33 166.67 60 1.20 1.20 200 200 400 175 1.0 Unit MHz MHz % ns ns ps ps ps ps ms Fall Time[3] Output to Output Skew on rising edges[3] Delay, REFIN Rising Edge to Measured at VDD/2 from REFIN to any output REF Rising Edge[3] Device to Device Skew[3] Period Jitter[3] PLL Lock Time[3] Measured at VDD/2 on the REF pin of the device (pin 1) Measured at Fout < 133.33 MHz, loaded outputs, 15-pF load Stable power supply, valid clocks presented on REFIN Switching Waveforms Figure 2. Duty Cycle Timing t1 t2 VDD/2 Figure 3. All Outputs Rise/Fall Time 2.0V 0.8V t3 2.0V 0.8V t4 3.3V 0V OUTPUT Figure 4. Output-Output Skew OUTPUT VDD/2 OUTPUT t5 VDD/2 Document #: 38-07249 Rev. *C Page 4 of 7 [+] Feedback CY2303 Switching Waveforms (continued) Figure 5. Input-Output Propagation Delay VDD/2 INPUT FBK t6 VDD/2 Figure 6. Device-Device Skew FBK, Device 1 VDD/2 FBK, Device 2 t7 VDD/2 Test Circuits Test Circuit # 1 VDD 0.1 F OUTPUTS CLK OUT C LOAD GND Ordering Information Ordering Code Pb-free CY2303SXC CY2303SXCT CY2303SXI CY2303SXIT 8-Pin 150-mil SOIC 8-Pin 150-mil SOIC - Tape and Reel 8-Pin 150-mil SOIC 8-Pin 150-mil SOIC - Tape and Reel Commercial Commercial Industrial Industrial Package Type Operating Range Document #: 38-07249 Rev. *C Page 5 of 7 [+] Feedback CY2303 Package Diagram Figure 7. 8-Pin (150-Mil) SOIC S8 8 Lead (150 Mil) SOIC - S08 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 0.150[3.810] 0.157[3.987] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. 5 8 SZ08.15 LEAD FREE PKG. 0.189[4.800] 0.196[4.978] SEATING PLANE 0.010[0.254] 0.016[0.406] X 45 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0~8 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 51-85066-*C Document #: 38-07249 Rev. *C Page 6 of 7 [+] Feedback CY2303 Document History Page Document Title: CY2303 Phase-Aligned Clock Multiplier Document Number: 38-07249 REV. ** *A *B *C ECN 110514 121852 390413 2568533 Orig. of Change SZV RBI RGL AESA Submission Date 01/07/02 12/14/02 08/10/05 09/23/08 Description of Change Change from Spec number: 38-01036 to 38-07249 Power up requirements added to Operating Conditions Information Added Lead-free devices Added typical values for jitter Updated template. Removed part number CY2303SC and CY2303SI from Selector Guide table. Removed part number CY2303SC, CY2303SCT, CY2303SI, and CY2303SIT. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com PSoC Solutions General Low Power/Low Voltage Precision Analog LCD Drive CAN 2.0b USB psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb (c) Cypress Semiconductor Corporation, 2002-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-07249 Rev. *C Revised September 23, 2008 Page 7 of 7 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback |
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